Address modification by main/control store boundary register in a microprogrammed processor

ABSTRACT

An address check boundary (ACB) register is initialized in accordance with the total amount of control/main storage with common addressing and with the relative amounts of control and main storage for the purpose of: 1. PROVIDING THE HIGHER ORDER BITS OF CONTROL STORE ADDRESS THUS PERMITTING FEWER BITS IN THE MICROPROGRAM SUPPLIED CONTROL STORE ADDRESS WITH RESULTING REDUCTION IN THE CONTROL WORD SIZE; 2. MODIFYING THE ACB supplied higher order bits and/or the microprogram supplied address bits where required; 3. SUPPLYING THE BOUNDARY ADDRESS BETWEEN CONTROL/MAIN STORE TO INITIATE AN ERROR SIGNAL IF MAIN STORE IS ACCESSED WHEN CONTROL STORE SHOULD HAVE BEEN ACCESSED AND VICE VERSA; 4. PROVIDING DATA REGARDING THE TYPE (INTERNAL - EXTERNAL) AND AMOUNT OF MAIN STORAGE AND REGARDING THE SYSTEM TYPE - SIMPLEX (ONE PROCESSOR) OR DUPLEX (TWO PROCESSORS).

United States Patent Dunbar, Jr. et al.

[ 1 Mar. 21, 1972 [$4] ADDRESS MODIFICATION BY MAIN/CONTROL STORE BOUNDARY 5' 4""? g w a fg gg b smtant xammerar war us aum A MICROPROGRAMMED Attorney-Hanifin and Jancin and John C. Black 172] Inventors: Robert G. Dunbar, Jr., Apalachin; Knrl K. [57] ABSTRACT Wollllck, bolh f An address check boundary (ACB) register is initialized in ac- {73' Ass-gnu. amnion Bush. Mum Crpo" cordance with the total amount of control/main storage with "on Armonk N Y common addressing and with the relative amounts of control and main storage for the purpose of: [2 Filed! IN'- 1970 1. Providing the higher order bits of control store address thus permitting fewer bits in the microprogram supplied [2i] Appl' 29226 control store address with resulting reduction in the control word size; [52] U.S.Cl ..340/l72.5 2. Modifying the ACB supplied higher order bits and/or [51] Int. Cl. ..G06t 9/20 the microprogram supplied address bits where required; [58] Field of Search ..340/l72.5; 235/157 3. Supplying the boundary address between gnt rollmz in store to initiate an error signal if main store is accessed when [56] Rgfgrencgs Cit d control store should have been accessed and vice versa;

4. Providing data regarding the type (internal-external) and UNlTED STATES PATENTS amount of main storage and regarding the system type 3 340 539 g 9 7 Sims 340 2 V DP XXwJZLQW S FJBF F1"E!LQW9PLF S@; 3,377,624 4/1968 Nelson et al.. ..340l172.5 4 Claims, 74 Drawing Figures 3,496,551 2/1970 Driscoll et al ..340/l72.5 3,533,077 /1970 Bell et a1 ..340/l72.5

96E [22.4 (22,5 968 96K I a Mi mun swan OR REGISTER mi in 5 do??? u2.o

store a WORK w -CLT 96 -lIA|lt SIORE ACBLS ICILL- OR E}- h 16 OR t A I ACBO. 4-7 1cm 1 A o ii i ABBLS AcaM-i AC8 9034) COMPARE a Y 1 g g gcsggs 940 945 930,, 956 :Eikfi wmss CHECK 9S4 95l]b "2114 SE AC8 COMPARE En BEST urn x1 REGISTER I EXT IJiST DEC 12 BYTE 1 M EXT DEST BYTEl 953 RESET 942 2 TIME DELAYF- 2 1E"; I CYCLE I I 945 k 94;

945 944 945 *Q FLI mm mm SIORE ACCESSHE ADDRESS WEEK ACB REGISTER AND CONTROLS i133 PAIENTEDM/xm I972 SHEET D2 BF 56 (FROM FIG. 2i)

FIG. 2a

LOCAL FIG. 2b

FIG. 2e

FIG. 2h

FIG.

SWITCHES FROM LATCH 63m (HG. 2c)

STORE ""AooaEss'" ASSEMBLER 1 FORCE SELECT CHANNELGEZ:

H? ipr EXTERNAL REGISTER ADDRESS ASSEMBLER CHANNEL 1 ECHANNEL 2 AECHANNEL 3 ECHANNEL 4 CONTROLS B LOCAL STORE SE LR COM PARE FIG. 2b

SHEET PAIENTEUmz: I972 T60 P.L 1

m 8 LS A LOCAL STORE EXTERNAL ASSEMBLER A COMPARE ,EBI

F/B ASM A DEST BUFFER BUFFER BUFFER M gg EXTERNAL r REGISTERS B DECODE DESTINATION 175 LOOK AHEAD F A DECODE Q: 150 A LS AooR DECODE CHANNEL 4 mm a CHANNEL t HI 8:

T0 TRAP AND PRIORITY CONTROL 12T. FIG. 2i

EXT REG DECODE Ea DEST ADDRESS :2

REGISTER PATENTEUHARZI I972 3.651.475

sum sum 56 FIG. 2c

8888:888888u8u8u OR OR OR OR A REG| STER 1 2 8 a && & aaaaaaaaa 00R 10R 20R 50R F T C REGISTER 215 CROSSBu SHIFT 8 226 GATING GATING PATENTEUMARZI I972 3.651.475

sum as or 56 FIG. 2d

aaa-aaaaaaaaa OR OR OR B REG ISTER I I l l aaaaaaaa BRANCH CIRCUITS CS/MS SDBI DRIVERS CROSS 8| GATING SHIFT 8: 327

GATING INVALID DEClMAL DIGIT CHECK PATENTEDHAR21 I972 SHEET CB [1F 56 FIG. 2e

AC8 REGISTER a CONTROLS 1n mu SHEEI UTUF 56 LATC SD80 PRE'ASSENBLY HES DIAGNOSTIC CONTROL PORTION 1 -mm N2. N5 (FIG. 2e)

REGISTER FIG. 2f

soaoasssuau &

OR o OR a 1 a 5 OR a a GE PROTECT SYSTEM cl ocK 1 I l as i SYSTEM MASTER CLOCK m OSCILLATOR CYCLE LENGTH T0 CONTROL POWTS PAIENIEUMAMI I972 3,551,475

sum 08 HF 56 TRUE 195 OMPLEME E51 DRIVERS i z REegsTER '1 2 PATENTEDMARZI I972 3.651 ,475

sum 09 0F 56 LOGICAL LOGICAL PARITY CHECK GENERATOR D ECIMAL COR RECT CONTROLS EBIO EBI BACKUP REGISTERS FIG. 2h

FIG. 23

PATENTEDMARZI 1972 3.651.475

SHEET 10 0F 56 Q m 146D TRAP a PRIORITY CONTROLS m j J M m us 102 100 MAIN STORAGE CONTROL STORAGE 1b EVEN lo EVEN I a 1 DR 2-" g J DATA E c c OUT $060 a m f 19g 104 MAIN SfTORAGE CONTROL STORAGE lb opo 10 000 f SECONDARY :7 omsuosnc FUNCTIONS PATENTEDMARZI I912 3.651.475

SHEET 110F56 0 TIME I80 0 TIME DLY CYCLE 1 TIME 1 TIME DLY -0SC u me o nus on CYCLE 2 TIME -osc mvsm guow onne onus OTINEDL 21o HIIIE CYCLE um um 2m znnsnn -osc FIG. 4

5s 050mm +o me new -mvem 050 --0 TIME nun +CLOCK sum RST-- +0 me me ns CYCLE -0 was VARIABLE cvcu: +1 +RESET CLOCK +1 TIME DELAY -225nsCYCLE- --nms DELAY 21o"; CYCLE +2 TIME -2TIME 2 ms new 2 TIME 0am FIG. 3 

1. For use in a data processing system of the type in which a microprogram control storage unit and a main storage unit are provided for storing control words and data, the control words being assigned initial addresses irrespective of storage unit capacities beginning with the high order address value of the maximum available control unit size, the combination comprising a common addressing means for accessing both storage units, the main storage unit being accessed by low order physical addresses and the control storage unit being accessed by immediately higher order physical addresses, an address check boundary register including first and second data fields indicative respectively of the storage capacity of each storage unit and of the physical address boundary between the storage units, means for forming initial control word addresses assigned to selected control words, means controlled by the address check boundary register data fields and by at least part of each initial control word address for producing the physical address of the control word, and means for setting the common addressing means to the physical address for accessing the control word.
 2. The combination set forth in claim 1 further comprising means for forming assigned main storage addresses and for setting the common addressing means to the assigned main storage addresses for accessing main storage words.
 3. The combination set forth in claim 2 further comprising means for comparing each main storage address and each physical control word address set into the common addressing means with the address boundary to determine whether or not the correct storage unit is being addressed.
 4. The combination set forth in claim 3 further comprising means for producing an error signal when the incorrect storage unit has been addressed. 